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ADP1043A
Table 84. Register 0x59—OUTAUX Rising Edge Timing (OUTAUX Pin)
Bits
[7:0]
Name
t 13
R/W
R/W
Description
This register contains the eight MSBs of the 12-bit t 13 time. This value is always used with the top
four bits of Register 0x5A, which contains the four LSBs of the t 13 time. Each LSB corresponds to
5 ns resolution.
Table 85. Register 0x5A—OUTAUX Rising Edge Setting (OUTAUX Pin)
Bits
[7:4]
Name
t 13
R/W
R/W
Description
These bits contain the four LSBs of the 12-bit t 13 time. This value is always used with the eight
bits of Register 0x59, which contains the eight MSBs of the t 13 time. Each LSB corresponds to 5 ns
resolution.
3
Modulate enable
R/W
1 = PWM modulation acts on the t 13 edge.
0 = no PWM modulation of the t 13 edge.
2
t 13 sign
R/W
1 = negative sign. Increase of PWM modulation moves t 13 right.
0 = positive sign. Increase of PWM modulation moves t 13 left.
[1:0]
Reserved
R/W
Reserved. Set these bits to 00 for normal operation.
Table 86. Register 0x5B—OUTAUX Falling Edge Timing (OUTAUX Pin)
Bits
[7:0]
Name
t 14
R/W
R/W
Description
This register contains the eight MSBs of the 12-bit t 14 time. This value is always used with the top
four bits of Register 0x5C, which contains the four LSBs of the t 14 time. Each LSB corresponds to
5 ns resolution.
Table 87. Register 0x5C—OUTAUX Falling Edge Setting (OUTAUX Pin)
Bits
[7:4]
Name
t 14
R/W
R/W
Description
These bits contain the four LSBs of the 12-bit t 14 time. This value is always used with the eight
bits of Register 0x5B, which contains the eight MSBs of the t 14 time. Each LSB corresponds to 5 ns
resolution.
3
Modulate enable
R/W
1 = PWM modulation acts on the t 14 edge.
0 = no PWM modulation of the t 14 edge.
2
t 14 sign
R/W
1 = negative sign. Increase of PWM modulation moves t 14 right.
0 = positive sign. Increase of PWM modulation moves t 14 left.
1
Regulate with
OUTAUX
R/W
1 = control loop PWM modulation is regulated by OUTAUX. When this bit is set, the CS1 blanking
signal is synchronized with OUTAUX.
0 = control loop PWM modulation is regulated by OUTA, OUTB, OUTC, OUTD, SR1, and SR2
(normal mode).
0
Reserved
R/W
Reserved. Set this bit to 0 for normal operation.
Table 88. Register 0x5D—OUTx and SR x Pin Disable Setting
Bits
7
6
5
4
3
2
1
0
Name
OUTAUX disable
SR2 disable
SR1 disable
OUTD disable
OUTC disable
OUTB disable
OUTA disable
GO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
Description
Setting this bit disables the OUTAUX output.
Setting this bit disables the SR2 output.
Setting this bit disables the SR1 output.
Setting this bit disables the OUTD output.
Setting this bit disables the OUTC output.
Setting this bit disables the OUTB output.
Setting this bit disables the OUTA output.
This bit latches in all registers from Address 0x3F to Address 0x5D. This bit prevents the PWM
timing from being temporarily incorrect, if changing PWM timing while the power supply is on.
This bit also latches in any changes made to Register 0x31 (VS3 voltage setting).
Rev. 0 | Page 57 of 72
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